This invention relates to a semiconductive memory device, and more particularly, to a write-in control for a synchronous semiconductive memory device.
In general, it is necessary to carry out read-out and write-in operations at a high speed in a semiconductive memory device in proportion to accelerating of central processing unit (CPU). In order to carry out the read-out and the write-in operations at the high speed in the semiconductive memory device, a conventional semiconductive memory device is disclosed in Japanese Patent Publication (JP-A) Tokkai Sho 61-148692 (148692/1986) and will be referred as a first conventional semiconductive memory device. The first conventional semiconductive memory device has an internal pipe-line structure. The first conventional semiconductive memory device divides a address access path into a plurality of stages on the read-out operation to carry out the read-out operation in a time division fashion, in order to shorten-an-cycle time. It is necessary to write data in a sense amplifier within a shortened cycle time on the write-in operation.
Another conventional semiconductive memory device is disclosed in Japanese Patent Publication (JP-A) Tokkai Hei 1-137492 (137492/1989) and will be referred as a second conventional semiconductive memory device. In order to shorten a write-in cycle time, the second conventional semiconductive memory device comprises a plurality of buffers which are arranged in parallel. The buffers are operated with different timings, respectively, in order to transfer in turn outputs of the buffers.
However, it is difficult to carry out the write-in operation at the high speed in each of the first and the second conventional semiconductive memory devices, as will be described later.